CPU Architecture & Instruction Sets Flashcards
7 cards from real CCP practice questions. Tap to flip, then mark Knew It or Still Learning — missed cards come back until you master them.
Read the first 7 CPU Architecture & Instruction Sets flashcards as text
Which cache write policy writes data to both the cache and main memory simultaneously on every write?
Answer: Write-through
Write-through policy updates both the cache and main memory on every write operation, ensuring memory consistency at the cost of higher memory bus traffic.
What is the purpose of Translation Lookaside Buffer (TLB) in a CPU?
Answer: To cache virtual-to-physical address translations, speeding up memory access
The TLB is a small hardware cache of recent virtual-to-physical address translations, reducing the overhead of walking the page table on every memory access.
In a pipelined CPU, what causes a 'structural hazard'?
Answer: Two instructions requiring the same hardware resource at the same time
A structural hazard occurs when two or more instructions need the same physical hardware resource (like a single memory port or ALU) simultaneously, preventing their concurrent execution.
What distinguishes a 'reduced instruction set' (RISC) approach in terms of instruction execution time?
Answer: Most instructions are designed to execute in a single clock cycle
RISC designs target single-cycle execution for most instructions by using simple, uniform instruction formats and load/store memory access patterns, enabling efficient pipelining.
What is 'speculative execution' in modern CPU design?
Answer: Executing instructions before it is certain they will be needed, based on predictions
Speculative execution allows the CPU to execute instructions ahead of confirmed need (e.g., after a predicted branch), discarding results if the speculation proves incorrect.
Which component of a CPU is responsible for performing arithmetic and logical operations?
Answer: Arithmetic Logic Unit (ALU)
The Arithmetic Logic Unit (ALU) performs all arithmetic operations (addition, subtraction) and logical operations (AND, OR, NOT) on binary data.
What is 'Amdahl's Law' used to predict in parallel computing?
Answer: The maximum speedup achievable by parallelizing a program, limited by its sequential fraction
Amdahl's Law states that the maximum speedup from parallelism is limited by the fraction of the program that must remain sequential, quantified as 1/(1-P) where P is the parallelizable fraction.