Free BEE Bachelor of Electrical Engineering Digital Logic and Microprocessors Questions and Answers — Questions and Answers
Question 1: A digital circuit with four inputs must produce a HIGH output only when an odd number of its inputs are HIGH. Which of the following single logic gates is most suitable for this application?
- A 4-input AND gate
- A 4-input OR gate
- A 4-input XOR gate (Correct answer)
- A 4-input NAND gate
Correct answer: A 4-input XOR gate
A multi-input Exclusive-OR (XOR) gate inherently functions as a parity checker. It produces a HIGH output (logic 1) if the number of HIGH inputs is odd, and a LOW output (logic 0) if the number of HIGH inputs is even. This makes it the ideal single gate for implementing an odd-parity detector.
Question 2: Which of the following statements best describes the primary operational difference between a D latch and a D flip-flop?
- A latch is level-triggered, meaning its output can change whenever the enable/clock signal is active, whereas a flip-flop is edge-triggered, changing its output only on a specific transition of the clock signal. (Correct answer)
- A flip-flop has a feedback path to store data, while a latch does not.
- A latch is constructed from NAND gates, while a flip-flop is constructed from NOR gates.
- A flip-flop can store two bits of data, while a latch can only store one bit.
Correct answer: A latch is level-triggered, meaning its output can change whenever the enable/clock signal is active, whereas a flip-flop is edge-triggered, changing its output only on a specific transition of the clock signal.
The fundamental distinction between a latch and a flip-flop is how they are triggered. A latch is level-triggered, making it 'transparent' when the enable signal is at its active level (e.g., HIGH); the output will follow any changes at the input. A flip-flop is edge-triggered, meaning it only samples the input and changes its output at the precise moment of a clock transition (either rising or falling edge), which provides better synchronization in sequential circuits.
Question 3: What is the primary architectural difference that distinguishes a Von Neumann architecture from a Harvard architecture in microprocessors?
- The use of a RISC versus a CISC instruction set.
- The number of processing cores available.
- The speed of the system clock.
- The organization of memory and buses for instructions and data. (Correct answer)
Correct answer: The organization of memory and buses for instructions and data.
The key difference lies in the memory structure. A Von Neumann architecture uses a single, shared memory and a common bus for both program instructions and data. In contrast, a Harvard architecture uses physically separate memories and separate buses for instructions and data, which allows the CPU to fetch an instruction and access data simultaneously, potentially overcoming the 'Von Neumann bottleneck'.
Question 4: An 8-bit digital system uses the two's complement method to represent signed integers. What is the correct binary representation for the decimal value -100?
- 01100100
- 10011100 (Correct answer)
- 10011011
- 11100100
Correct answer: 10011100
To find the two's complement representation of -100 in 8 bits: 1. Find the binary representation of positive 100: 64 + 32 + 4 = 100, which is 01100100. 2. Invert all the bits (one's complement): 10011011. 3. Add 1 to the result: 10011011 + 1 = 10011100.
Question 5: Which of the following is a primary advantage of using CMOS (Complementary Metal-Oxide-Semiconductor) logic gates over TTL (Transistor-Transistor Logic) gates?
- Significantly faster switching speed in all applications.
- Greater immunity to electrostatic discharge (ESD).
- Much lower static power dissipation. (Correct answer)
- Simpler fabrication process.
Correct answer: Much lower static power dissipation.
The main advantage of CMOS technology is its very low static power dissipation. In a static state (output not changing), one of the complementary MOSFETs in a CMOS gate is always off, creating a high-impedance path from the power supply to ground and consuming negligible current. TTL gates, in contrast, draw a considerable amount of current even when their state is not changing.
Question 6: A microprocessor-based system is designed such that peripheral devices are accessed using the same instructions (e.g., MOV, LOAD, STORE) and occupy the same address space as the main memory. What is this I/O handling technique called?
- Memory-mapped I/O (Correct answer)
- Port-mapped I/O
- Direct Memory Access (DMA)
- Interrupt-driven I/O
Correct answer: Memory-mapped I/O
This technique is called Memory-Mapped I/O (MMIO). In MMIO, the I/O devices are mapped into the system's memory address space. This allows the CPU to use the same address bus and the same set of instructions to access both memory and I/O devices, simplifying the instruction set and programming model. This contrasts with Port-mapped I/O (also called isolated I/O), which uses a separate address space and special I/O instructions (like IN and OUT).
Free BEE Bachelor of Electrical Engineering Digital Logic and Microprocessors Questions and Answers
A digital circuit with four inputs must produce a HIGH output only when an odd number of its inputs are HIGH.
Which of the following single logic gates is most suitable for this application?