BEE Digital Logic and Design 2 — Questions and Answers
Question 1: Which minimization technique uses a graphical map to simplify Boolean expressions by grouping adjacent 1s?
- Quine-McCluskey method
- Karnaugh map (Correct answer)
- Shannon expansion
- Petrick's method
Correct answer: Karnaugh map
A Karnaugh map (K-map) is a graphical tool that simplifies Boolean expressions by visually grouping adjacent cells containing 1s into power-of-2 groups.
Question 2: In a D flip-flop, what is the output Q after a rising clock edge if D = 0 and the current Q = 1?
- Q remains 1
- Q becomes 0 (Correct answer)
- Q toggles to 0 then back to 1
- Q is undefined
Correct answer: Q becomes 0
A D flip-flop captures the value of D on the active clock edge, so Q takes the value of D (0) regardless of its previous state.
Question 3: A full adder produces a Sum and a Carry-out. What is the Carry-out when A=1, B=1, Cin=1?
- 0
- 1 (Correct answer)
- Undefined
- Same as Sum
Correct answer: 1
With A=1, B=1, Cin=1, the total is 3 (binary 11), so Carry-out=1 and Sum=1.
Question 4: Which of the following represents a hazard in combinational logic circuits?
- Propagation delay being zero
- A momentary glitch in the output during input transitions (Correct answer)
- A permanent stuck-at fault
- Fan-out exceeding the drive capability
Correct answer: A momentary glitch in the output during input transitions
A hazard is a momentary spurious output glitch caused by unequal propagation delays along different signal paths during input transitions.
Question 5: What is the primary advantage of a synchronous counter over an asynchronous (ripple) counter?
- Uses fewer flip-flops
- All flip-flops are clocked simultaneously, eliminating cumulative delay (Correct answer)
- Operates at lower power
- Counts in Gray code by default
Correct answer: All flip-flops are clocked simultaneously, eliminating cumulative delay
In a synchronous counter all flip-flops share the same clock, so state transitions occur simultaneously and cumulative ripple delay is eliminated.
Question 6: Which logic family is characterized by the lowest static power dissipation at zero frequency?
- TTL
- ECL
- CMOS (Correct answer)
- DTL
Correct answer: CMOS
CMOS dissipates nearly zero static power because in steady state either the PMOS or NMOS transistor is off, blocking DC current flow.
Question 7: A 3-to-8 line decoder with an active-low enable (EN') is used. If EN'=1, what is the state of all outputs?
- All outputs are HIGH (Correct answer)
- All outputs are LOW
- Only the selected output is HIGH
- The decoder operates normally
Correct answer: All outputs are HIGH
With active-low enable asserted high (disabled), all decoder outputs remain in their inactive (HIGH) state since active-low outputs go HIGH when not selected.
BEE Digital Logic and Design 2
Which minimization technique uses a graphical map to simplify Boolean expressions by grouping adjacent 1s?