BEE Bachelor of Electrical Engineering Analog and Digital Electronics Questions and Answers — Questions and Answers
Question 1: An ideal operational amplifier (op-amp) is configured as a non-inverting amplifier. Which of the following characteristics is NOT representative of this ideal model?
- Zero output impedance
- Infinite input impedance
- Zero common-mode rejection ratio (CMRR) (Correct answer)
- Infinite open-loop voltage gain
Correct answer: Zero common-mode rejection ratio (CMRR)
An ideal op-amp is characterized by infinite open-loop gain, infinite input impedance, and zero output impedance. It also has an infinite Common-Mode Rejection Ratio (CMRR), meaning it perfectly rejects any voltage common to both inputs. Therefore, a zero CMRR is not a characteristic of an ideal op-amp; in fact, it represents the worst-case scenario where common-mode signals are amplified as much as differential signals.
Question 2: A digital designer needs to simplify the Boolean expression Y = (A + B)'. According to De Morgan's theorems, which of the following expressions is equivalent?
- Y = A' + B'
- Y = A' . B' (Correct answer)
- Y = (A . B)'
- Y = A . B
Correct answer: Y = A' . B'
De Morgan's second theorem states that the complement of a sum (OR operation) is equal to the product (AND operation) of the complements. Therefore, the expression (A + B)' is equivalent to A' . B'.
Question 3: In a BJT common-emitter amplifier configuration, what is the typical phase relationship between the input signal at the base and the output signal at the collector?
- The output is in phase with the input.
- The output leads the input by 90 degrees.
- The output is 180 degrees out of phase with the input. (Correct answer)
- The output lags the input by 90 degrees.
Correct answer: The output is 180 degrees out of phase with the input.
The common-emitter amplifier is an inverting amplifier. This means that as the input voltage at the base increases, the collector current increases, causing a larger voltage drop across the collector resistor. This results in a decrease in the collector voltage. Consequently, the output signal at the collector is 180 degrees out of phase with the input signal at the base.
Question 4: A technician is troubleshooting a Class B push-pull amplifier and observes distortion on the output waveform precisely at the zero-crossing point. What is the most likely cause of this issue?
- Thermal runaway
- Clipping distortion
- Harmonic distortion
- Crossover distortion (Correct answer)
Correct answer: Crossover distortion
Crossover distortion occurs in Class B amplifiers because there is a small region around the zero-crossing point where both transistors are turned off. This happens because the input signal must overcome the base-emitter voltage (around 0.7V for silicon transistors) before a transistor starts to conduct. This 'deadband' causes a flat spot on the output waveform as it crosses zero.
Question 5: Which type of Analog-to-Digital Converter (ADC) operates by sequentially testing each bit from the most significant bit (MSB) to the least significant bit (LSB) to find the digital equivalent of an analog signal?
- Flash ADC
- Dual-Slope ADC
- Successive-Approximation ADC (Correct answer)
- Delta-Sigma ADC
Correct answer: Successive-Approximation ADC
A Successive-Approximation Register (SAR) ADC works by using a binary search algorithm. It starts by setting the MSB to 1 and compares the resulting analog voltage (from an internal DAC) to the input signal. Based on the comparison, the bit is either kept or cleared, and the process repeats for the next bit until the LSB is determined. This method allows for a good balance between speed and resolution.
Question 6: A JK flip-flop is configured with both J and K inputs held high (connected to logic 1). If a clock signal is applied, what will be the behavior of the Q output?
- The output will be permanently set to 1.
- The output will toggle its state on each clock pulse. (Correct answer)
- The output will be permanently reset to 0.
- The output state will be indeterminate.
Correct answer: The output will toggle its state on each clock pulse.
When both J and K inputs of a JK flip-flop are held high, the flip-flop is in 'toggle' mode. In this mode, the output (Q) will invert its current state on the active edge of each clock pulse. This is a key feature that distinguishes the JK flip-flop from an SR flip-flop, as it provides a predictable outcome for the '1, 1' input condition.
BEE Bachelor of Electrical Engineering Analog and Digital Electronics Questions and Answers
An ideal operational amplifier (op-amp) is configured as a non-inverting amplifier.
Which of the following characteristics is NOT representative of this ideal model?